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February 2007
(R)
AS6C1008
128K X 8 BIT LOW POWER CMOS SRAM
FEATURES
Access time :55ns Low powe r consumption: Operating current:10 mA (TYP.) Standby current: 1 A (TYP .) Single 2.7V ~ 5.5V po we r supply Fully Compatible with all Competitors 5V product Fully Compatible with all Competitors 3.3V product Fully s tatic operation Tri-state output Data retention voltage : 1.5V (MIN.) All products are ROHS Compliant Package : 32-pin 450 mil SOP 32-pin 600 mil P-DIP 32-pin 8mm x 20mm TSOP-I 32-pin 8mm x 13.4mm sTSOP 36-ball 6mm x 8mm TFBGA
GENERAL DESCRIPTION
The AS6C1008 is a 1,048,576 -bit low powe r CMOS static random access me mory organized as 131,072 words by 8 bits . It is fabricated using ve ry high performance, high reliability CMOS technolo gy. Its sta ndby current is stable within the ra nge of operating temperature. The AS6C1008 is well designed for very low power system applications, a nd particula rly well suited for battery back-u p non-volatile memory a pplication. The AS6C1008 operates from a single power supply of 2.7V ~ 5.5V. .
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
SYMBOL DESCRIPTION Addres s Inputs Da ta Inputs /Outputs Chip Enable Inputs Write Enable Input Output Enable Input Pow er Supply G round No C onnection A0 - A16 DQ0 - DQ7 CE#, CE2 WE# OE# VCC V SS NC
Vcc Vss
A0-A16
DECODER
128Kx8 MEMORY ARRAY
DQ0-DQ7
I/O DATA CIRCUIT
COLUMN I/O
CE# CE2 WE# OE#
CONTROL CIRCUIT
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Alliance Memory Inc.
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February 2007
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AS6C1008
128K X 8 BIT LOW POWER CMOS SRAM
PIN CONFIGURATION
NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SOP/P-DIP 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Vcc A15 CE2 WE# A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 A1 1 A9 A8 A1 3 WE # CE 2 A1 5 Vc c NC A1 6 A1 4 A1 2 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE # A10 CE # DQ7 DQ6 DQ5 DQ4 DQ3 Vss DQ2 DQ1 DQ0 A0 A1 A2 A3
AS6C1008
AS6C1008
T S OP -I/sTSOP
A B C D E F G H
A0 DQ4 DQ5 Vss Vcc DQ6
A1 A2
CE2 WE# NC
A3 A4 A5
A6 A7
A8 DQ0 DQ1 Vcc Vss
NC
NC
DQ2 A15 DQ3 A13 A14
DQ7 OE# CE# A16 A9 A10 A11 A12
1
2
3 4 TFBGA
5
6
.
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Alliance Memory Inc.
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February 2007
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AS6C1008
128K X 8 BIT LOW POWER CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER Terminal Voltage with Respect to VSS Operating Temperature Storage Temperature Power Dissipation DC Output Current Soldering Temperature (under 10 sec) SYMBOL VTERM TA TSTG PD IOUT TSOLDER -40 to 85(I grade) -65 to 150 1 50 260 RATING -0.5 to 7.0 0 to 70(C grade) UNIT V C C W mA C
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE Standby Output Disable Read Write
Note:
CE# H X L L L
CE2 X L H H H
OE# X X H L X
WE# X X H H L
I/O OPERATION High-Z High-Z High-Z DOUT DIN
SUPPLY CURRENT ISB1 ISB1 ICC,ICC1 ICC,ICC1 ICC,ICC1
H = VIH, L = VIL, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
SYMBOL TEST CONDITION MIN. PARAMETER Supply Voltage VCC 2.7 *1 Input High Voltage VIH 0.7*Vcc *2 Input Low Voltage VIL - 0.2 VCC VIN VSS Input Leakage Current ILI -1 VCC VOUT VSS, Output Leakage ILO -1 Current Output Disabled Output High Voltage VOH IOH = -1mA 2.2 Output Low Voltage VOL IOL = 2mA Cycle time = Min. CE# = VIL and CE2 = VIH, - 55 ICC II/O = 0mA Average Operating Cycle time = 1s Power supply Current CE#0.2V and CE2VCC-0.2V, ICC1 II/O = 0mA other pins at 0.2V or VCC-0.2V CE# VCC-0.2V C* Standby Power ISB1 Supply Current or CE20.2V I* *C=Commercial temperature/I= Industrial temperature
TYP. 3.0 2.7 10
*4
MAX. 5.5 VCC+0.3 0.6 1 1 0.4 60
UNIT V V V A A V V mA
1 1 1
10 20 50
mA A A
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February 2007
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AS6C1008
128K X 8 BIT LOW POWER CMOS SRAM
Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP.) and TA = 25C
CAPACITANCE (TA = 25, f = 1.0MHz)
PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN.
Note : These parameters are guaranteed by device characterization, but not production tested.
-
MAX 6 8
UNIT pF pF
AC TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL =30pF + 1TTL, IOH/IOL = -1mA/2mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ* AS6C1008-55 MIN. MAX. 55 55 55 30 10 5 20 20 10 AS6C1008-55 MIN. MAX. 55 50 50 0 45 0 25 0 5 20 UNIT ns ns ns ns ns ns ns ns ns UNIT ns ns ns ns ns ns ns ns ns ns
*These parameters are guaranteed by device characterization, but not production tested.
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Alliance Memory Inc.
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February 2007
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AS6C1008
128K X 8 BIT LOW POWER CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
tRC Address tAA Dout Previous Data Valid tOH Data Valid
READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5)
tRC Address tAA CE# tACE CE2 OE# tOLZ tOE tOH tOHZ tCHZ Data Valid High-Z
tCLZ Dout High-Z
Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low., CE2 = high. 3.Address must be valid prior to or coincident with CE# = low, CE2 = high; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured 500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.
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Alliance Memory Inc.
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February 2007
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AS6C1008
128K X 8 BIT LOW POWER CMOS SRAM
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)
tWC Address tAW CE# tCW CE2 tAS WE# tWHZ Dout (4) High-Z tDW Din tDH TOW (4) tWP tWR
Data Valid
WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6)
tWC Address tAW CE# tAS tCW CE2 tWP WE# tWHZ Dout (4) High-Z tDW Din tDH tWR
Data Valid
Notes : 1.WE#, CE# must be high or CE2 must be low during all address transitions. 2.A write occurs during the overlap of a low CE#, high CE2, low WE#. 3.During a WE#controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured 500mV from steady state.
02/February/07, v 1.0
Alliance Memory Inc.
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February 2007
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AS6C1008
128K X 8 BIT LOW POWER CMOS SRAM
DATA RETENTION CHARACTERISTICS
PARAMETER VCC for Data Retention Data Retention Current SYMBOL VDR IDR TEST CONDITION CE# VCC - 0.2V or CE2 0.2V C** I** 0 tRC* MIN. 1.5 TYP. 0.5 0 MAX. 5.5 1 3 UNIT V A ns ns
VCC = 1.5V CE# VCC - 0.2V or CE2 0.2V
See Data Retention Chip Disable to Data tCDR Waveforms (below) Retention Time Recovery Time tR tRC* = Read Cycle Time C=Commercial temp/I = Industrial temp**
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) (CE# controlled)
VDR 1.5V Vcc Vcc(min.) tCDR CE# VIH CE# Vcc-0.2V Vcc(min.) tR VIH
Low Vcc Data Retention Waveform (2) (CE2 controlled)
VDR 1.5V Vcc Vcc(min.) tCDR CE2 CE2 0.2V VIL VIL Vcc(min.) tR
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Alliance Memory Inc.
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February 2007
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AS6C1008
128K X 8 BIT LOW POWER CMOS SRAM
PACKAGE OUTLINE DIMENSION
32 pin 450 mil SOP Package Outline Dimension
SYM.
UNIT
INCH.(BASE) 0.118 (MAX) 0.004(MIN) 0.111(MAX) 0.016(TYP) 0.008(TYP) 0.817(MAX) 0.445 0.005 0.555 0.012 0.050(TYP) 0.0347 0.008 0.055 0.008 0.026(MAX) 0.004(MAX) o o 0 -10
MM(REF) 2.997 (MAX) 0.102(MIN) 2.82(MAX) 0.406(TYP) 0.203(TYP) 20.75(MAX) 11.303 0.127 14.097 0.305 1.270(TYP) 0.881 0.203 1.397 0.203 0.660 (MAX) 0.101(MAX) o o 0 -10
A A1 A2 b c D E E1 e L L1 S y
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February 2007
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AS6C1008
128K X 8 BIT LOW POWER CMOS SRAM
32 pin 600 mil P-DIP Package Outline Dimension
UNIT SYM.
INCH(BASE) 0.001 (MIN) 0.150 0.005 0.018 0.005 1.650 0.005 0.600 0.010 0.544 0.004 0.100 (TYP) 0.640 0.020 0.130 0.010 0.075 0.010 0.070 0.005
MM(REF) 0.254 (MIN) 3.810 0.127 0.457 0.127 41.910 0.127 15.240 0.254 13.818 0.102 2.540 (TYP) 16.256 0.508. 3.302 0.254 1.905 0.254 1.778 0.127
A1 A2 B D E E1 e eB L S Q1
Note : D/E1/S dimension do not include mold flash.
02/February/07, v 1.0
Alliance Memory Inc.
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February 2007
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AS6C1008
128K X 8 BIT LOW POWER CMOS SRAM
32 pin 8mm x 20mm TSOP-I Package Outline Dimension
SYM.
UNIT
INCH(BASE) 0.047 (MAX) 0.004 0.002 0.039 0.002 0.008 + 0.002 - 0.001 0.005 (TYP) 0.724 0.004 0.315 0.004 0.020 (TYP) 0.787 0.008 0.0197 0.004 0.0315 0.004 0.003 (MAX) o o 0 5
MM(REF) 1.20 (MAX) 0.10 0.05 1.00 0.05 0.20 + 0.05 -0.03 0.127 (TYP) 18.40 0.10 8.00 0.10 0.50 (TYP) 20.00 0.20 0.50 0.10 0.08 0.10 0.076 (MAX) o o 0 5
A A1 A2 b
c D E e HD L L1 y
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Alliance Memory Inc.
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February 2007
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AS6C1008
128K X 8 BIT LOW POWER CMOS SRAM
32 pin 8mm x 13.4mm sTSOP Package Outline Dimension
HD
c L
1 32
12 (2x)
12 (2x)
e
16 17
"A"
D Seating Plane
b
E
y
12 (2X)
16
17
GAUGE PLANE A A2 c 0.254 0 A1 SEATING PLANE L L1 12 (2X)
"A" DETAIL VIEW
1 32
SYM.
UNIT
INCH(BASE) 0.049 (MAX) 0.005 0.002 0.039 0.002 0.008 0.01 0.005 (TYP) 0.465 0.004 0.315 0.004 0.020 (TYP) 0.5280.008 0.0197 0.004 0.0315 0.004 0.003 (MAX) o o 0 5
MM(REF) 1.25 (MAX) 0.130 0.05 1.00 0.05 0.200.025 0.127 (TYP) 11.80 0.10 8.00 0.10 0.50 (TYP) 13.40 0.20. 0.50 0.10 0.8 0.10 0.076 (MAX) o o 0 5
A A1 A2 b c D E e HD L L1 y
02/February/07, v 1.0
Alliance Memory Inc.
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February 2007
AS6C1008
128K X 8 BIT LOW POWER CMOS SRAM
36 ball 6mm x 8mm TFBGA Package Outline Dimension
02/February/07, v 1.0
Alliance Memory Inc.
Page 12 of 14
February 2007
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AS6C1008
128K X 8 BIT LOW POWER CMOS SRAM
ORDERING INFORMATION
Ordering Codes
Operating Speed Temp ns Commercial ~ 0 C to 70 C 55 Industrial ~ -40C to 85 C 55 Industrial ~ -40C to 85 C 55 Industrial ~ -40C to 85 C 55 Industrial ~ -40C to 85 C 55
Alliance AS6C1008-55PCN AS6C1008-55SIN AS6C1008-55TIN AS6C1008-55STIN AS6C1008-55BIN
Organization VCC range 128K X 8 128K X 8 128K X 8 128K X 8 128K X 8 2.7-5.5V 2.7-5.5V 2.7-5.5V 2.7-5.5V 2.7-5.5V
Package 32pin 600mil PDIP 32pin 450mil SOP 32pin TSOP-I (8 x 20 mm) 32pin sTSOP (8 x 13.4 mm) 36pin TFBGA (6mm x 8mm)
Part numbering system
AS6C 1008 - 55 X X N
Package Options: P = 32 pin 600 mil P-DIP low Device S = 32 pin 450 mil SOP power Number T = 32 pin TSOP-I (8mm x 20 mm) SRAM 10 = 1M Access ST = 32 pin sTSOP (8 x 13.4 mm) prefix 08 = by 8 Time B = 36 ball 6 x 8mm TFBGA
Temperature Range: C = Commercial N = Lead (0C to +70 C) Free ROHS I = Industrial Compliant (-40 to +85 C) Part
02/February/07, v 1.0
Alliance Memory Inc.
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February 2007
AS6C1008
128K X 8 BIT LOW POWER CMOS SRAM
(R)
(R)
Alliance Memory, Inc. 1116 South Amphlett, #2, San Mateo, CA 94402 Tel: 650-525-3737 Fax: 650-525-0449 www.alliancememory.com
Copyright (c) Alliance Memory All Rights Reserved Part Number: AS6C1008 Document Version: v. 1.0
(c) Copyright 2003 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
02/February/07, v 1.0
Alliance Memory Inc.
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